 
module top(
  input clk_50M,
  input reset,
  output [4:0] led,
  
  output D26,//uart out
 
//  5V
//GND
output C26,
output F24,
input  F27,
input  H21,
input  E26,
input  J24,
input  K27,
input  K22,

output                   mem_odt,
output                   mem_cs_n,
output                   mem_cke,
output           [13:0]  mem_addr,
output           [2:0]   mem_ba,
output                   mem_ras_n,
output                   mem_cas_n,
output                   mem_we_n,
output           [3:0]   mem_dm,
inout                    mem_clk,
inout                    mem_clk_n,
inout           [31:0]   mem_dq,
inout           [3:0]    mem_dqs,

input        USB3_UART_IN,
output       USB3_RST_OUT,
output       USB3_PCLK,
inout [31:0] USB3_DQ,
output [1:0] USB3_A,
output       USB3_SLCS_N,
output       USB3_SLWR_N,
output       USB3_SLOE_N,
output       USB3_SLRD_N,
output       USB3_PKTEND_N,
input        USB3_FLAGA,
input        USB3_FLAGB,
input        USB3_FLAGC,
input        USB3_FLAGD,
input        USB3_CMD_CLK,
input        USB3_CMD_DAT_U2F,
output       USB3_CMD_DAT_F2U,


  input dummy
);

reg sys_rst_n ;// && locked_sdram && locked_cpu && locked_vga;

assign D26 = USB3_UART_IN;


reg [20:0] reset_delay;
always @(posedge clk_50M or negedge reset) begin
  if (!reset) begin
    reset_delay <= 0;
     sys_rst_n <= 0;
  end else begin
    reset_delay <= reset_delay+1'b1;
     if(reset_delay[20])begin
        sys_rst_n <= 1;
     end
  end
end


assign led[0] = flg;
assign led[1] = 1;
assign led[2] = 1;
assign led[3] = 1;
assign led[4] = 1;

reg [31:0] cnt;
reg flg;
always @(posedge clk_50M or negedge sys_rst_n) begin
  if (!sys_rst_n) begin
    cnt <= 0;
    flg <= 1;
  end else begin
    cnt <= cnt+1'b1;
     if(cnt==32'd50000000)begin
        cnt <= 0;
        flg <= ~flg;
     end
  end
end







debugger_usb3 debugger_usb3_inst (
    .clk(clk_50M),
    .clk_50M(clk_50M),
    .reset_n(sys_rst_n),// && USB3_RST_OUT

    .USB3_UART_IN    (USB3_UART_IN    ),
    .USB3_RST_OUT    (USB3_RST_OUT    ),
    .USB3_PCLK       (USB3_PCLK       ),
    .USB3_DQ         (USB3_DQ         ),
    .USB3_A          (USB3_A          ),
    .USB3_SLCS_N     (USB3_SLCS_N     ),
    .USB3_SLWR_N     (USB3_SLWR_N     ),
    .USB3_SLOE_N     (USB3_SLOE_N     ),
    .USB3_SLRD_N     (USB3_SLRD_N     ),
    .USB3_PKTEND_N   (USB3_PKTEND_N   ),
    .USB3_FLAGA      (USB3_FLAGA      ),
    .USB3_FLAGB      (USB3_FLAGB      ),
    .USB3_FLAGC      (USB3_FLAGC      ),
    .USB3_FLAGD      (USB3_FLAGD      ),
    .USB3_CMD_CLK    (USB3_CMD_CLK    ),
    .USB3_CMD_DAT_U2F(USB3_CMD_DAT_U2F),
    .USB3_CMD_DAT_F2U(USB3_CMD_DAT_F2U),

    .dummy(dummy)
);



endmodule
